Cybersecurity and Quantum Biomedical Interdisciplinary Technologies (Cy-QuBIT) Lab

This project will develop circuit design techniques for energy-recovery circuits and a library of such design cells to facilitate low-power implementation of block cipher for mobile Internet-of-Things (IoT) devices, where reducing power consumption is critical. The design challenge is to produce low-energy, lightweight, and secure devices, which are also resistant against malicious attacks that use power consumption traces to extract private or sensitive information.

This project will provide a set of energy recovery (ER) principles for low-energy and differential power analysis (DPA)-resistant IoT devices. The research objectives are: (i) to investigate information leakage in ER circuits and propose mitigation methodologies; (ii) to investigate and develop a low-energy and DPA-resistant ER standard cell library and semi-custom design flow for lightweight cryptographic circuits; and (iii) to investigate and develop power clock generation and distribution, and silicon prototyping to evaluate energy dissipation and the DPA-resistance of ER-based crypto circuits.

Publications:

MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA

Milad Tanavardi Nasab, Himanshu Thapliyal and Garrett S Rose, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.33, 2025

Modern applications like IoT devices, AI, and automotive applications widely use FPGAs. However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this paper, two low-power and CPA-resistant hybrid CMOS/MTJ logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single-output, and the second one is multi-output. The simulation results show that compared to the state-of-the-art secure CLB counterpart (secured configurable logic block, sCLB, by Zooker et al.), the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of BNN, compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and AES SBOX. Also, this resiliency has been investigated for different TMRs and supply voltages.

Energy-Efficient Adiabatic MTJ/CMOS-Based CLB for Non-Volatile FPGA

Milad Tanavardi Nasab, Wu Yang and Himanshu Thapliyal, IEEE 24th International Conference on Nanotechnology (NANO), Gijon, Spain, 2024, pp. 517-522

High flexibility, infinite reconfigurability, and fast design-to-market of FPGAs make them a promising platform for modern applications, such as IoT, medical, and automotive applications. Energy and area limitations are challenging in these applications since many of these applications have limited power and hardware resources. Accordingly, the energy- and area-efficient design of FPGAs is of great importance. In this paper, an adiabatic non-volatile hybrid CMOS/MTJ logic-in-memory-based configurable logic block (CLB) has been proposed and compared to its state-of-the-art counterparts. The simulation results show that the proposed design has 98%, 98%, 97%, 97%, 96%, and 92% lower energy consumption compared to CMOS counterparts for frequencies of 1, 2.5, 5, 10, 20, and 40 MHz. Also, compared to its adiabatic counterparts, the proposed design has at least 74%, 70%, 69%, 69%, and 46% lower energy consumption for frequencies of 1, 2.5, 5, 10, and 20 MHz, respectively. Also, the proposed design has at least 74% fewer transistors compared to its counterparts. Furthermore, the energy saving of the proposed design for different tunnel magnetoresistance (TMR) is almost consistent. In addition, the proposed design keeps its superiority in energy saving over its counterparts for different power supply voltages.

Energy-Efficient Power Analysis Attack Resilient Adiabatic MTJ-Based Nonvolatile CLB

Milad Tanavardi Nasab, Wu Yang and Himanshu Thapliyal, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, TN, USA, 2024, pp. 469-474

Energy efficiency and security against side-channel attacks (like power analysis attacks) in modern and battery-operated applications like IoT and medical applications are vital. On the other hand, FPGAs are widely used as a hardware platform for these applications. Accordingly, energy-efficient and power analysis attack-resilient design for FPGA is required. This paper proposes an energy-efficient power analysis attack-resilient adiabatic nonvolatile hybrid MTJ/CMOS LiM-based CLB. The simulation results show that the proposed design has 98.72%, 98.72%, 98.69%, 98.61%, 98.43%, and 98.11% (at least 84.69%, 84.74%, 84.28%, 83.19%, 80.70%, and 77%) lower energy consumption compared to its CMOS counterpart (adiabatic counterparts) for frequencies of 1, 2.5, 5, 10, 20, and 40 MHz, respectively. Also, the proposed design keeps its energy consumption superiority for different TMR and power supply voltages, compared to its counterparts. The NED and NSD values of different designs have been calculated and used as power analysis attack-resiliency metrics. The results show that the proposed design has 1053x and 1628x (at least 23x and 14x) lower NED and NSD values compared to its CMOS counterpart (adiabatic counterparts). Furthermore, the NED and NSD values of the proposed design stay in the same range (10-4) for different frequencies, power supply voltages, and TMR.

Dual rail adiabatic circuit design offers hardware-level protection against side-channel power analysis attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) attacks. While considerable attention has been given to synthesizing logic tree-based adiabatic circuits, comparatively little attention has been given to generating truly secure circuit variants. This paper presents preliminary results for a secure dual rail adiabatic synthesis tool based on Binary Decision Diagrams (BDDs). The tool demonstrates encouraging performance in matching known optimal transistor counts for several basic logic gates, in addition to providing improvement over existing works on established benchmarks.

Energy Efficient CLB Design Based on Adiabatic Logic for IoT Applications

Wu Yang, Milad Tanavardi Nasab and Himanshu Thapliyal, Electronics, v.13, 2024.

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T.

A Novel Energy-Efficient Sinusoidal Power Clocking-based Writing Circuitry for the hybrid CMOS/MTJ architecture

 Wu Yang, Amit Degada, and Himanshu Thapliyal, IEEE Transactions on Magnetics, v.60, 2024

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) offers a promising solution for low-power and high-density memory due to its compatibility with CMOS, higher density, scalable nature, and non-volatility. However, the higher energy required to write bit cells has remained a key challenge for its adaptation into battery-operated smart handheld devices. The existing low-energy writing solutions require additional complex control logic mechanisms, further constraining the available area. In this research, we propose a solution to design energy-efficient write circuits by incorporating two techniques together. First, we propose the sinusoidal power clocking mechanism replacing the DC power supply in the conventional CMOS design. Second, we propose three LUT-based control logic circuits and one write circuit to reduce the area and further minimize energy dissipation. The experimental results are verified over the case study implementations of 4x4 STT-MRAM macro designed using bit cell configurations: (i) 1T-1MTJ and (ii) 4T-2MTJ. The post-layout simulation for the frequency range from 250 kHz to 6.25 MHz, the write circuit, which uses the proposed LUT-based control logic circuits and a write driver with a sinusoidal power supply, shows a more than 65.05% average energy saving compared to the CMOS counterpart. Furthermore, the write circuit, which uses the proposed 6T write driver with the sinusoidal power supply, shows an improvement in energy saving by more than 70.60% compared to the CMOS counterpart. We also verified that the energy-saving performance remains relatively consistent with the change in temperature and the Tunnelling Magnetoresistance (TMR) ratio.

Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security

Zachary Kahleifeh and Himanshu Thapliyal, IEEE Transactions on Consumer Electronics, v.69, 2023

Consumer electronics require secure operation in the face of the many emerging threat vectors. One hardware security primitive is the Physically Unclonable Function (PUF). PUFs utilize process variations to give a device a digital fingerprint and are an important resource in secure hardware. One drawback of the addition of secure hardware is the increased energy consumption. In this paper, we look to design a secure, low-energy PUF using both adiabatic logic and Magnetic Tunnel Junctions (MTJ). Adiabatic logic reduces the dynamic energy consumption of the PUF while the MTJs offer a near zero-leakage power, nonvolatile memory option. MTJs have two stable states depending on the magnetization direction of the free layer with respect to that of the fixed layer. Hence, the proposed adiabatic/MTJ PUF offers two modes of operation depending on the orientation of the MTJ. Our proposed adiabatic/MTJ PUF has average reliability of 97.07% and 96.97% between the two modes of operation while taking into account temperature, supply voltage, and TMR variations. The two modes of our proposed PUF consume 5.2 fJ and 5.1 fJ per bit.

Low-Power Adiabatic/MTJ LIM-Based XNOR/XOR Synapse and Neuron for Binarized Neural Networks

Milad Tanavardi Nasab and Himanshu Thapliyal, IEEE 23rd International Conference on Nanotechnology (NANO), Jeju City, Korea, Republic of, 2023, pp. 649-654

Using binarized neural network (BNN) as an alternative to the conventional convolutional neural network is a promising candidate to answer the demand of using human brain-inspired in applications with limited hardware and power resources, such as biomedical devices, IoT edge sensors, and other battery-operated devices. Using nonvolatile memory elements like MTJ devices in a LiM-based architecture can eliminate the need to access and use external memory which can significantly reduce the power consumption and area overhead. In addition, by using adiabatic-based designs, a significant part of the consumed power can be recovered to the power source which leads to a huge reduction in power consumption which is vital in applications with limited power and hardware resources. In this paper by using nonvolatile MTJ devices in a LiM architecture and using adiabatic-based circuits, an XNOR/XOR synapse and neuron is proposed. The proposed design offers 97% improvement in comparison with its state-of-the-art counterparts in case of power consumption. Also, it achieves at least 7% lower area compared to other counterparts which makes the proposed design a promising candidate for hardware implementation of BNNs.

2-Phase Adiabatic Logic for Low-Energy and CPA-Resistant Implantable Medical Devices

Amit Degada and Himanshu Thapliyal, IEEE Transactions on Consumer Electronics,  vol. 68, no. 1, pp. 47-56, Feb. 2022.

Designing a low-energy and secure lightweight cryptographic coprocessor is the primary design constraint for modern wireless Implantable Medical Devices (IMDs). The lightweight cryptographic ciphers are the preferred cryptographic solution for low-energy encryption. This article proposes 2-SPGAL, the 2-phase sinusoidal clocking implementation of Symmetric Pass Gate Adiabatic Logic (SPGAL) for IMDs. The proposed 2-SPGAL is energy-efficient and secure against the Correlation Power Analysis (CPA) attack. The proposed 2-SPGAL was evaluated with the integration of synchronous resonant Power Clock Generators (PCGs): (i) 2N2P-PCG, and (ii) 2N-PCG. The case study implementation of one round of PRESENT-80 encryption using 2-SPGAL, with 2N2P-PCG integrated into the design, shows an average of 47.50% of energy saving compared to its CMOS counterpart, over the frequency range of 50 kHz to 250 kHz. The same 2-SPGAL based case study, with 2N-PCG integrated into the design, shows 51.18% of an average energy saving compared to its CMOS counterpart, over 50 kHz to 250 kHz. Further, the 2-SPGAL based PRESENT-80 one round shows an average energy saving of 16.62% and 28.90% respectively for 2N2P-PCG and 2N-PCG integrated into the design compared to existing 2-phase adiabatic logic called 2-EE-SPFAL. We also subjected PRESENT-80 design of 2-SPGAL and CMOS against CPA attack. The 2-SPGAL, with 2N2P-PCG and 2N-PCG, integrated into one round of PRESENT80 design protects the encryption key. However, the encryption key was successfully revealed in one round of PRESENT-80 design using CMOS logic. Therefore, the proposed 2-SPGAL logic can be useful to design energy-efficient and CPA resilient Implantable Medical Devices (IMDs).

Single-Rail Adiabatic Logic for Energy-Efficient and CPA-Resistant Cryptographic Circuit in Low-Frequency Medical Devices

Amit Degada and Himanshu Thapliyal, IEEE Open Journal of Nanotechnology, vol. 3, pp. 1-14, 2022.

Designing energy-efficient and secure cryptographic circuits in low-frequency medical devices are challenging due to low-energy requirements. Also, the conventional CMOS logic-based cryptographic circuits solutions in medical devices can be vulnerable to side-channel attacks (e.g. correlation power analysis (CPA)). In this article, we explored single-rail Clocked CMOS Adiabatic Logic (CCAL) to design an energy-efficient and secure cryptographic circuit for low-frequency medical devices. The performance of the CCAL logic-based circuits was checked with a power clock generator (2N2P-PCG) integrated into the design for the frequency range of 50 kHz to 250 kHz. The CCAL logic gates show an average of approximately 48% energy-saving and more than 95% improvement in security metrics performance compared to its CMOS logic gate counterparts. Further, the CCAL based circuits are also compared for energy-saving performance against dual-rail adiabatic logic, 2-EE-SPFAL, and 2-SPGAL. The adiabatic CCAL gates save on an average of 55% energy saving compared to 2-EE-SPFAL and 2-SPGAL over the frequency range of 50 kHz to 250 kHz. To check the efficacy of CCAL to design a larger cryptographic circuit, we implemented a case-study design of a Substitution-box (S-box) of popular lightweight PRESENT-80 encryption. The case-study implementation (2N2P-PCG integrated into the design) using CCAL shows more than 95% energy saving compared to CMOS for the frequency 50 kHz to 125 kHz and around 60% energy saving at frequency 250 kHz. At 250 kHz, compared to the dual-rail adiabatic designs of S-box based on 2-EE-SPFAL and 2-SPGAL, the CCAL based S-box shows 32.67% and 11.21% of energy savings, respectively. Additionally, the CCAL logic gate structure requires a lesser number of transistors compared to dual-rail adiabatic logic. The case-study implementation using CCAL saves 45.74% and 34.88% transistor counts compared to 2-EE-SPFAL and 2-SPGAL. The article also presents the effect of varying tank capacitance in 2N2P-PCG over energy efficiency and security performance. The CCAL based case-study was also subjected against CPA. The CCAL-based S-box case study successfully protects the revelation of the encryption key against the CPA attack, However, the key was revealed in CMOS-based case-study implementation.

Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics

Zachary Kahleifeh and Himanshu Thapliyal, IEEE Consumer Electronics Magazine, vol. 11, no. 1, pp. 57-64, 1 Jan. 2022.

Smart consumer electronic devices are mostly area constrained and operate on a limited battery supply and therefore, have tight energy budgets. Lightweight cryptography (LWC) such as PRESENT-80 allows for minimal area usage and low energy for secure operations. However, CMOS implemented LWCs are vulnerable to side-channel attacks such as correlation power analysis (CPA). Adiabatic logic is an emerging circuit design technique that can reduce energy consumption and be CPA resistant. Many existing adiabatic logic families use a four-phase clocking scheme which pays a large area penalty. Thus, in this article, we introduce 2-EE-SPFAL, a two-phase clocking scheme implementation of an existing adiabatic family known as EE-SPFAL. To show the applicability of 2-EE-SPFAL, we construct a two-phase clock generator that remains energy efficient and secure. From 100 kHz to 25 MHz, our results show an average energy saving of 76.5% to 21.3% between CMOS and 2-EE-SPFAL. As a case study, we performed a CPA attack on both the CMOS and 2-EE-SPFAL implementation of PRESENT-80 and determined that the CMOS key could be retrieved while the adiabatic key was kept hidden.

Approximate Adiabatic Logic for Low-Power and Secure Edge Computing

Wu Tang and Himanshu Thapliyal, IEEE Consumer Electronics Magazine, vol. 11, no. 1, pp. 88-94, 1 Jan. 2022

Approximate computing is a promising approach for error-tolerant applications running on the Internet-of-Things edge devices to reduce power consumption. However, approximate computation is susceptible to side-channel attacks, such as attacks based on differential power analysis (DPA). Energy efficiency could be further enhanced by applying adiabatic logic in approximate edge computing while increasing its protection against the side-channel attacks. As a case study, we are presenting two approximate adders based on adiabatic logic to illustrate the benefits of approximate computation combined with adiabatic logic. The proposed approximate adders leverage the dual-rail property of adiabatic logic to minimize the overall size and further decrease energy consumption. In this article, the first design is true sum approximate adder (TSAA), whereas the second design is True Carry-out Approximate Adder (TCAA). There are fewer transistors in adiabatic logic-based TSAA and TCAA compared to CMOS-based accurate mirror adder (AMA). At 12.5-MHz operating frequency and 45-nm technology node, the adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48% and energy savings of 90.80% and 90.96% in comparison with the standard CMOS AMA. We also show that both designs proposed are more secure against DPA attacks.

EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices

Zachary Kahleifeh and Himanshu Thapliyal, Sensors, 21(22):7651, 2021.

Internet of Things (IoT) devices have strict energy constraints as they often operate on a battery supply. The cryptographic operations within IoT devices consume substantial energy and are vulnerable to a class of hardware attacks known as side-channel attacks. To reduce the energy consumption and defend against side-channel attacks, we propose combining adiabatic logic and Magnetic Tunnel Junctions to form our novel Energy Efficient-Adiabatic CMOS/MTJ Logic (EE-ACML). EE-ACML is shown to be both low energy and secure when compared to existing CMOS/MTJ architectures. EE-ACML reduces dynamic energy consumption with adiabatic logic, while MTJs reduce the leakage power of a circuit. To show practical functionality and energy savings, we designed one round of PRESENT-80 with the proposed EE-ACML integrated with an adiabatic clock generator. The proposed EE-ACML-based PRESENT-80 showed energy savings of 67.24% at 25 MHz and 86.5% at 100 MHz when compared with a previously proposed CMOS/MTJ circuit. Furthermore, we performed a CPA attack on our proposed design, and the key was kept secret.

Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices

S. Dinesh Kumar and Himanshu Thapliyal, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 16, no. 3:34, pp.1-18, 2020

Internet of Things (IoT) devices have stringent constraints on power and energy consumption. Adiabatic logic has been proposed as a novel computing platform to design energy-efficient IoT devices. Physically Unclonable Functions (PUFs) is a promising paradigm to solve security concerns such as Integrated Circuit (IC) piracy, IC counterfeiting, and the like. PUFs have shown great promise for generating the secret bits that can be used in the secure systems in an inexpensive way. However, designing a reliable PUF along with energy-efficiency is a big challenge. Therefore, for energy-efficient and reliable PUFs, we are proposing a novel energy-efficient adiabatic logic-based PUF structure. The proposed adiabatic PUF uses energy recovery concept to achieve high energy efficiency and uses the time ramp voltage to exhibit the reliable start-up behavior. The channel length of the transistors play a major role in controlling manufacturing variations. So, in this article, the circuit simulations are performed with 180nm and 45nm Complementary metal-oxide-semiconductor (CMOS) technology in a Cadence Spectre simulator to analyze the impact of channel length variations. The proposed adiabatic PUF has worst-case reliability of 96.84% and 99.6% with temperature variations at 180nm and 45nm CMOS technology, respectively. Further, the proposed adiabatic PUF consumes 1.071fJ/bit-per cycle at 180nm CMOS technology and 0.08fJ/bit-per cycle at 45nm CMOS technology.

Master's and PhD Dissertations:

Post-Layout Evaluation of Adiabatic Logic for Energy Efficiency and CPA Resistance

Jun-Cheng Chin, Master's Thesis, University of Tennessee, 2024.

The Internet of Things (IoT) has become commonplace in society, but it has been demonstrated that many IoT systems are vulnerable to significant security exploits. This necessitates the need for a closer examination of IoT security. IoT design prerequisites are low power consumption and an emphasis on smaller die areas for increased production yield. Security on the software level typically provides adequate protection but there are hardware-level exploits that are difficult or impossible to counteract. Booting attacks, eavesdropping and interference, and Side-Channel Attacks (SCA) are exploits deployed against IoT devices on the hardware level. To combat these vulnerabilities, several lightweight hardware encryption techniques such as PRESENT-80, in particular, are developed for their lower power usage and smaller device footprint. However, studies show that PRESENT-80 is still vulnerable to SCA or power analysis attacks. Literature on improved PRESENT-80 circuits provides SCA resistance but the trade-offs are often an increase in device area and distinguishable power usage patterns. A recently developed adiabatic circuit technique introduced as Energy Efficient Positive Feedback Adiabatic Logic (EE-SPFAL) shows promise of resistance against SCA and consumes lower power compared to traditional CMOS digital circuits. However, the simulation results are solely presented through the schematic layer without the inclusion of post-layout simulation. This work aims to fill the gap by providing the layout design of EE-SPFAL standard cells and a prototype of 1 Round PRESENT-80 S-box using EE-SPFAL. Post-layout Correlation Power Analysis (CPA) attacks and energy consumption analysis are conducted and compared with the conventional CMOS circuit. In addition, this work aims to show the effects of parasitic capacitance within inter-logic cell routing on SCA resistance and highlight the limitations of schematic-only simulations against CPA attacks. This work is designed using open-source CAD tools from Efabless/Google with Skywater 130nm technology.

Energy-Efficient and Secure Hardware Using Adiabatic Logic and Non-Volatile MTJ Devices

Zachary Kahleifeh, Doctoral Dissertation, University of Kentucky, 2023.

Internet of Things (IoT) is a collection of devices that exchange data through a network to implement complex applications. IoT devices increase the quality of life of their user base which has a wide variety such as the medical field, consumer electronics, and the manufacturing sector. However, IoT devices have several challenges that need to be overcome namely, security and energy consumption. The threat vector that IoT devices face is growing and includes the following threats, the leakage of information through a side-channel attack known as the Correlation Power Analysis (CPA), authentication, piracy, etc. There are many countermeasures to CPA attacks, however, many of these countermeasures consume substantial energy which makes them non-ideal for IoT devices which are typically battery operated. In this thesis, we have explored the use of a novel, low-energy design technique known as adiabatic logic and an emerging memory technology known as Magnetic Tunnel Junctions (MTJ) to design ultra-low-energy and CPA resistant circuits for use in IoT devices. Adiabatic logic is an ultra-low energy circuit design technique that utilizes power clocks to supply and recover charge from a circuit. Adiabatic logic is typically constructed using a 4-phase power clock however, the area and complexity of the power clock generator is a design limitation. Thus, the first contribution of this thesis is the conversion of an existing adiabatic logic family known as Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) into a functional and energy-efficient 2-phase implementation. 2-EE-SPFAL has less complex routing and less complex power clock design when compared to EE-SPFAL and is energy-efficient compared to standard CMOS. Furthermore, 2-EE-SPFAL has uniform power consumption regardless of data transition and thus is shown to be secure against power analysis attacks. Adiabatic logic reduces the dynamic energy consumption of a circuit but as the technology node decreases through sub 45nm the leakage power of an integrated circuit becomes a limiting factor. To that end, the second contribution of this thesis is the design of a hybrid adiabatic and MTJ circuit architecture. One of the main advantages of MTJs is the near-zero leakage power they consume which is essential as technology nodes scale down. To create an ultra-low energy circuit, we combine the dynamic energy savings of adiabatic logic with the leakage power savings of MTJs to create Energy-Efficient Adiabatic CMOS/MTJ Logic (EE-ACML). We also show that EE-ACML is CPA resistant by implementing a lightweight cryptographic cipher utilizing EE-ACML and unsuccessfully stealing the encryption keys when performing a CPA attack. Authentication, privacy, and secure key generation are important considerations when designing IoT devices. One security primitive that can aid in solving the aforementioned issues is the Physically Unclonable Function (PUF). The third contributionof this thesis is the design of a hybrid adiabatic/MTJ PUF. The proposed PUF saves energy by utilizing the energy recovery of adiabatic logic as well as the reduced leakage power with the implementation of the MTJs. The source of manufacturing variation within the proposed PUF is dominated by the variation of the MTJs. The clock generator of an adiabatic circuit is an essential component of any adiabatic system. Adiabatic clock generators come in many forms based on the number of phases they produce. For example, a 2-phase clock generator can produce a 2-phase clock in the form of a sinusoidal waveform. Different adiabatic circuits are constructed using these different clock generators and are shown to be energy-efficient. However, there is a lack of comparison on clock generators in terms of both energy efficiency and security against power analysis attacks. Thus, we perform a comparative study on 2 and 4-phase clock generators to analyze the trade-offs between energy efficiency and security of adiabatic clock generators.

Designing Novel Hardware Security Primitives for Smart Computing Device

Amitkumar Degada, Doctoral Dissertation, University of Kentucky, 2022.

Smart computing devices are miniaturized electronics devices that can sense their surroundings, communicate, and share information autonomously with other devices to work cohesively. Smart devices have played a major role in improving quality of the life and boosting the global economy. They are ubiquitously present, smart home, smart city, smart girds, industry, healthcare, controlling the hazardous environment, and military, etc. However, we have witnessed an exponential rise in potential threat vectors and physical attacks in recent years. The conventional software-based security approaches are not suitable in the smart computing device, therefore, hardware-enabled security solutions have emerged as an attractive choice. Developing hardware security primitives, such as True Random Number Generator (TRNG) and Physically Unclonable Function (PUF) from electrical properties of the sensor could be a novel research direction. Secondly, the Lightweight Cryptographic (LWC) ciphers used in smart computing devices are found vulnerable against Correlation Power Analysis (CPA) attack. The CPA performs statistical analysis of the power consumption of the cryptographic core and reveals the encryption key. The countermeasure against CPA results in an increase in energy consumption, therefore, they are not suitable for battery operated smart computing devices. The primary goal of this dissertation is to develop novel hardware security primitives from existing sensors and energy-efficient LWC circuit implementation with CPA resilience. To achieve these. we focus on developing TRNG and PUF from existing photoresistor and photovoltaic solar cell sensors in smart devices Further, we explored energy recovery computing (also known as adiabatic computing) circuit design technique that reduces the energy consumption compared to baseline CMOS logic design and same time increasing CPA resilience in low-frequency applications, e.g. wearable fitness gadgets, hearing aid and biomedical instruments. The first contribution of this dissertation is to develop a TRNG prototype from the uncertainty present in photoresistor sensors. The existing sensorbased TRNGs suffer a low random bit generation rate, therefore, are not suitable in real-time applications. The proposed prototype has an average random bit generation rate of 8 kbps, 32 times higher than the existing sensorbased TRNG. The proposed lightweight scrambling method results in random bit entropy close to ideal value 1. The proposed TRNG prototype passes all 15 statistical tests of the National Institute of Standards and Technology (NIST) Statistical Test Suite with quality performance. The second contribution of this dissertation is to develop an integrated TRNG-PUF designed using photovoltaic solar cell sensors. The TRNG and PUF are mutually independent in the way they are designed, therefore, integrating them as one architecture can be beneficial in resource-constrained computing devices. We propose a novel histogram-based technique to segregate photovoltaic solar cell sensor response suitable for TRNG and PUF respectively. The proposed prototype archives approximately 34% improvement in TRNG output. The proposed prototype achieves an average of 92.13% reliability and 50.91% uniformity performance in PUF response. The proposed sensor-based hardware security primitives do not require additional interfacing hardware. Therefore, they can be ported as a software update on existing photoresistor and photovoltaic sensor-based devices. Furthermore, the sensor-based design approach can identify physically tempered and faulty sensor nodes during authentication as their response bit differs. The third contribution is towards the development of a novel 2-phase sinusoidal clocking implementation, 2-SPGAL for existing Symmetric Pass Gate Adiabatic Logic (SPGAL). The proposed 2-SPGAL logic-based LWC cipher PRESENT shows an average of 49.34% energy saving compared to baseline CMOS logic implementation. Furthermore, the 2-SPGAL prototype has an average of 22.76% better energy saving compared to 2-EE-SPFAL (2-phase Energy-Efficient-Secure Positive Feedback Adiabatic Logic). The proposed 2-SPGAL was tested for energy-efficiency performance for the frequency range of 50 kHz to 250 kHz, used in healthcare gadgets and biomedical instruments. The proposed 2-SPGAL based design saves 16.78% transistor count compared to 2-EE-SPFAL counterpart. The final contribution is to explore Clocked CMOS Adiabatic Logic (CCAL) to design a cryptographic circuit. Previously proposed 2-SPGAL and 2-EESPFAL uses two complementary pairs of the transistor evaluation network, thus resulting in a higher transistor count compared to the CMOS counterpart. The CCAL structure is very similar to CMOS and unlike 2-SPGAL and 2-EE-SPFAL, it does not require discharge circuitry to improve security performance. The case-study implementation LWC cipher PRESENT S-Box using CCAL results into 45.74% and 34.88% transistor count saving compared to 2-EE-SPFAL and 2-SPGAL counterpart. Furthermore, the case-study implementation using CCAL shows more than 95% energy saving compared to CMOS logic at frequency range 50 kHz to 125 kHz, and approximately 60% energy saving at frequency 250 kHz. The case study also shows 32.67% and 11.21% more energy saving compared to 2-EE-SPFAL and 2-SPGAL respectively at frequency 250 kHz. We also show that 200 fF of tank capacitor in the clock generator circuit results in optimum energy and security performance in CCAL.

Combining Approximate Computing and Adiabatic Logic for Low-Power and Energy-Efficient IoT Edge Computing

Wu Yang, Master's Thesis, University of Kentucky, 2021.

The growing data-intensive applications that run on IoT edge devices require the circuit to be low-power consumption and energy-efficient for limited resources. As conventional Complementary Metal-Oxide-Semiconductor (CMOS) scales down to the nanometer technology node, it reaches its limits, such as leakage and power consumption. Adiabatic logic and approximate computing are emerging techniques for the low-power circuit. Adiabatic logic can recycle energy which is a promising solution for building energy-efficient circuits. However, the power clock scheme and dual-rail structure of adiabatic logic increase the overall area. Power consumption is further reduced by applying approximate computing while reducing the complexity and size of the circuit. Therefore, to investigate the benefits of approximate computing combined with adiabatic logic, we propose two adiabatic logic based approximate adders. The proposed approximate adders use the advantage of dual-rail logic to shrink the overall size and reduce energy consumption. The two proposed designs are True Sum Approximate Adder (TSAA) and True Carry-out Approximate Adder (TCAA). TSAA approximates the Carryout based on the accurate Sum, and TCAA approximates the Sum based on the precise Carryout. We performed simulations using 45nm technology in Cadence Spectre. Comparing with CMOS based accurate mirror adder (AMA) at 100 MHz, a power-saving of 83.26% and energy saving of 66.54% in PFAL based TSAA (PFAL: Positive Feedback Adiabatic Logic) is achieved. Further, we achieved a power saving of 87.22% and an energy saving of 74.43% in PFAL based TCAA compared to CMOS based accurate mirror adder (AMA). It is illustrated that PFAL based TCAA consumes 24.0% less power and energy per cycle compared to PFAL based TSAA. Further, we have proposed the True Sum Approximate Adder (TSAA) and the True Carry-out Approximate Adder (TCAA) that are energy-efficient and secured against DPA attacks. At 12.5 MHz operating frequency and 45 nm technology node, the DPA-resistant adiabatic TSAA and TCAA achieved power savings of 95.4% and 95.48%, energy savings of 90.80%, and 90.96% in comparison with the standard CMOS AMA.