Books:

• Quantum Computing: Circuits, Systems, Automation and Applications”, Editors: Himanshu Thapliyal and Travis Humble, Published by Springer, Jan 204.

Journals Publications:

1. B. Gaur and H. Thapliyal, "Novel Optimized Designs of Modulo 2 n + 1 Adder for Quantum Computing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2024.341893

2. W. Yang, A. Degada and H. Thapliyal, "A Novel Energy-Efficient Sinusoidal Power Clocking-based Writing Circuitry for the hybrid CMOS/MTJ architecture," in IEEE Transactions on Magnetics, doi: 10.1109/TMAG.2024.3430120.

3. M. S. H. Onim, E. Rhodus and H. Thapliyal, "A Review of Context-Aware Machine Learning for Stress Detection," in IEEE Consumer Electronics Magazine, vol. 13, no. 4, pp. 10-16, July 2024, doi: 10.1109/MCE.2023.3278076.

4. M. S. H. Onim, H. Thapliyal, and E. K. Rhodus, “Utilizing Machine Learning for Context-Aware Digital Biomarker of Stress in Older Adults,” Information, vol. 15, no. 5, Art. no. 5, May 2024, doi: 10.3390/info15050274.

5. T. Cultice and H. Thapliyal, "Vulnerabilities and Attacks on CAN-Based 3D Printing/Additive Manufacturing," in IEEE Consumer Electronics Magazine, vol. 13, no. 1, pp. 54-61, Jan. 2024, doi: 10.1109/MCE.2023.3240849

6. T. Cultice, J. Clark, W. Yang, and H. Thapliyal, “A Novel Hierarchical Security Solution for Controller-Area-Network-Based 3D Printing in a Post-Quantum World,” Sensors, vol. 23, no. 24, Art. no. 24, Jan. 2023, doi: 10.3390/s23249886.

7. M. S. H. Onim, E. Rhodus and H. Thapliyal, "A Review of Context-Aware Machine Learning for Stress Detection," in IEEE Consumer Electronics Magazine, doi: 10.1109/MCE.2023.3278076.

8. D. Pal, V. Vanijja, H. Thapliyal, and X. Zhang, “What affects the usage of artificial conversational agents? An agent personality and love theory perspective,” Computers in Human Behavior, vol. 145, p. 107788, Aug. 2023, doi: 10.1016/j.chb.2023.107788.

9. R. Rohan, D. Pal, J. Hautamäki, S. Funilkul, W. Chutimaskul, and H. Thapliyal, “A systematic literature review of cybersecurity scales assessing information security awareness,” Heliyon, vol. 9, no. 3, p. e14234, Mar. 2023, doi: 10.1016/j.heliyon.2023.e14234.

10. Z. Kahleifeh, H. Thapliyal and S. M. Alam, "Adiabatic/MTJ based Physically Unclonable Function for Consumer Electronics Security," in IEEE Transactions on Consumer Electronics, 2022, doi: 10.1109/TCE.2022.3201247.

11. J. -C. Chin, H. Thapliyal and T. Cultice, "CAN Bus: The Future of Additive Manufacturing (3D Printing)," in IEEE Consumer Electronics Magazine, 2022, doi: 10.1109/MCE.2022.3216944.

12. T. Cultice and H. Thapliyal, “PUF-Based Post-Quantum CAN-FD Framework for Vehicular Security,” Information, vol. 13, no. 8, Art. no. 8, Aug. 2022, doi: 10.3390/info13080382.

13. D. Pal, P. Roy, C. Arpnikanondt, and H. Thapliyal, “The effect of trust and its antecedents towards determining users’ behavioral intention with voice-based consumer electronic devices,” Heliyon, vol. 8, no. 4, p. e09271, Apr. 2022, doi: 10.1016/j.heliyon.2022.e09271.

14. A. Cannavó, F. Lamberti, H. Thapliyal and R. Thawonmas, "Guest Editorial Introduction to the Special Section on Immersive Virtual Reality Simulation for Vehicular Technology," in IEEE Transactions on Vehicular Technology, vol. 71, no. 4, pp. 3397-3398, April 2022, doi: 10.1109/TVT.2022.3160625.

15. F. L. I. Dutsinma, D. Pal, P. Roy and H. Thapliyal, "Personality is to a Conversational Agent What Perfume is to a Flower," in IEEE Consumer Electronics Magazine, doi: 10.1109/MCE.2022.3180183.

16. R. Rohan, S. Funilkul, D. Pal and H. Thapliyal, "Humans in the Loop: Cybersecurity Aspects in the Consumer IoT Context," in IEEE Consumer Electronics Magazine, doi: 10.1109/MCE.2021.3095385.

17. A. Degada and H. Thapliyal, "2-Phase Adiabatic Logic For Low-Energy and CPA-Resistant Implantable Medical Devices," in IEEE Transactions on Consumer Electronics, doi: 10.1109/TCE.2022.3141342.

18. C. Labrado, H. Thapliyal, and S. P. Mohanty, “Fortifying Vehicular Security through Low Overhead Physically Unclonable Functions,” ACM J. Emerg. Technol. Comput. Syst., vol. 18, no. 1, pp. 1–18, Jan. 2022, doi: 10.1145/3442443.

19. A. Degada and H. Thapliyal, "Single-Rail Adiabatic Logic for Energy-Efficient and CPA-Resistant Cryptographic Circuit in Low-Frequency Medical Devices," in IEEE Open Journal of Nanotechnology, vol. 3, pp. 1-14, 2022, 

20. Z. Kahleifeh and H. Thapliyal, “EE-ACML: Energy-Efficient Adiabatic CMOS/MTJ Logic for CPA-Resistant IoT Devices,” Sensors, vol. 21, no. 22, p. 7651, Nov. 2021,

21. D. Pal, V. Vanijja, X. Zhang and H. Thapliyal, "Exploring the Antecedents of Consumer Electronics IoT Devices Purchase Decision: A Mixed Methods Study," in IEEE Transactions on Consumer Electronics, vol. 67, no. 4, pp. 305-318, Nov. 2021

22. W. Yang and H. Thapliyal, "Approximate Adiabatic Logic for Low-Power and Secure Edge Computing," in IEEE Consumer Electronics Magazine, vol. 11, no. 1, pp. 88-94, 1 Jan. 2022, doi: 10.1109/MCE.2021.3053908.

23. Z. Kahleifeh and H. Thapliyal, "Adiabatic Logic Based Energy-Efficient Security for Smart Consumer Electronics," in IEEE Consumer Electronics Magazine, vol. 11, no. 1, pp. 57-64, 1 Jan. 2022, doi: 10.1109/MCE.2020.3028046.

24. H. Thapliyal and S. P. Mohanty, "Physical Unclonable Function (PUF)-Based Sustainable Cybersecurity," in IEEE Consumer Electronics Magazine, vol. 10, no. 4, pp. 79-80, 1 July 2021, doi: 10.1109/MCE.2021.3065857.

25. R. K. Nath, H. Thapliyal, and T. S. Humble, “A Review of Machine Learning Classification Using Quantum Annealing for Real-World Applications,” SN COMPUT. SCI., vol. 2, no. 5, p. 365, Sep. 2021, doi: 10.1007/s42979-021-00751-0.

26. R. K. Nath and H. Thapliyal, “Machine Learning-Based Anxiety Detection in Older Adults Using Wristband Sensors and Context Feature,” SN COMPUT. SCI., vol. 2, no. 5, p. 359, Sep. 2021, doi: 10.1007/s42979-021-00744-z.

27. A. Degada and H. Thapliyal, "An Integrated TRNG-PUF Architecture Based on Photovoltaic Solar Cells," in IEEE Consumer Electronics Magazine, vol. 10, no. 4, pp. 99-105, 1 July 2021

28. H. Thapliyal, E. MuÑoz-Coreas, T. S. S. Varun and T. S. Humble, "Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 1045-1056, 1 April-June 2021

29. H. Thapliyal, K. Michael, S. P. Mohanty, M. B. Srinivas and M. K. Ganapathiraju, "Consumer Technology-Based Solutions for COVID-19," IEEE Consumer Electronics Magazine, vol. 10, no. 2, pp. 64-65, 1 March 2021, doi: 10.1109/MCE.2020.3040513.

30. R. K. Nath and H. Thapliyal, "Smart Wristband-Based Stress Detection Framework for Older Adults With Cortisol as Stress Biomarker,” IEEE Transactions on Consumer Electronics, vol. 67, no. 1, pp. 30-39, Feb. 2021, doi: 10.1109/TCE.2021.3057806.

31. S. D. Kumar, Z. Kahleifeh and H. Thapliyal, “Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design”, Springer Nature Computer Science, 2, 92 (2021). https://doi.org/10.1007/s42979-021-00482-2

32. R. Nath, H. Thapliyal and A. Caban-Holt, “Machine Learning Based Stress Monitoring in Older Adults Using Wearable Sensors and Cortisol as Stress Biomarker,” Journal of Signal Processing Systems, 2021. https://doi.org/10.1007/s11265-020-01611-5

33. H. Thapliyal, E. Munoz-Coreas and V. Khalus, “Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits”, Sustainable Computing: Informatics and Systems, 2020. https://doi.org/10.1016/j.suscom.2020.100457

34. C. Labrado, S. D. Kumar, R. Badhan, H. Thapliyal, and V. Singh, “Exploration of Solar Cell Materials for Developing Novel PUFs in Cyber-Physical Systems,” SN COMPUT. SCI., vol. 1, no. 6, p. 313, Sep. 2020, doi: 10.1007/s42979-020-00331-8.

35. Y. Takahashi, H. Koyasu, S. D. Kumar and H. Thapliyal, “Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function”, Springer Nature Computer Science, Vol. 1, Article 237, July 2020.

36. S.D. Kumar, H. Thapliyal, “Design of Adiabatic Logic Based Energy Efficient and Reliable PUF for IoT devices”, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 16, No. 3, Article 34, June 2020.

37. R. K. Nath, H. Thapliyal, A. Caban-Holt and S. P. Mohanty, " Machine Learning Based Solutions for Real-Time Stress Monitoring”, IEEE Consumer Electronics Magazine, vol. 9, no. 5, pp. 34-41, 1 Sept. 2020.

38. S.D. Kumar and H. Thapliyal, “Exploration of Non-Volatile MTJ/CMOS Circuits for DPA Resistant Embedded Hardware”, IEEE Transactions on Magnetics, vol. 55, no. 12, pp. 1-8, Dec. 2019, Art no. 3401308.

39. H. Thapliyal, S. Mohanty and S. Prowell, “Emerging Paradigms in Vehicular Cybersecurity", IEEE Consumer Electronics Magazine, vol. 8, no. 6, pp. 81-83, Nov. 2019

40. H. Thapliyal and E. Munoz-Coreas, “Design of Quantum Computing Circuits”, IEEE IT Professional, vol. 21, no. 6, pp. 22-26, Nov-Dec. 2019.

41. C. Labrado and H. Thapliyal, S. Prowell, and T. Kuruganti “Use of Thermistor Temperature Sensors for Cyber-Physical System Security”, Sensors, Vol. 19, No. 18, 3905, 2019.

42. C. Labrado and H. Thapliyal, "Hardware Security Primitives for Vehicles", IEEE Consumer Electronics Magazine, vol. 8, no. 6, pp. 99-103, Nov. 2019.

43. T.S. Humble, H. Thapliyal, E. Muñoz-Coreas, F.A. Mohiyaddin, and R.S. Bennink, “Quantum computing circuits and devices”, IEEE Design & Test, vol. 36, no. 3, pp. 69-94, June 2019.

44. S.D. Kumar, H. Thapliyal, and A. Mohammad, “EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card”, IEEE Transactions on Emerging Topics in Computing, vol. 7, no. 2, pp. 281-293, 1 April-June 2019. 

45. E. Munoz-Coreas and H. Thapliyal, “Quantum Circuit Design of A T-count Optimized Integer Multiplier,” IEEE Transactions on Computers, vol. 68, no. 5, pp. 729-739, May 2019.

46. C. Labrado and H. Thapliyal, “Design of a Piezoelectric Based Physically Unclonable Function for IoT Security,” IEEE Internet of Things Journal, vol. 6, no. 2, pp. 2770-2777, April 2019.

47. F. Sharifi, M.H. , Moaiyeri, H. Sharifi,  K.  Navi and H. Thapliyal, “On the design of quaternary arithmetic logic unit based on CNTFETs”, International Journal of Electronics Letters, Vol.7, No. 1, pp.221-232, 2019.

48. H. Thapliyal, "Internet of Things-Based Consumer Electronics: Reviewing Existing Consumer Electronic Devices, Systems, and Platforms and Exploring New Research Paradigms,” IEEE Consumer Electronics Magazine, vol. 7, no. 1, pp. 66-67, Jan. 2018.

49. E. Munoz-Coreas and H. Thapliyal, “T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 14 Issue 3, October 2018. Article No.: 36

50. H. Thapliyal, F. Sharifi, and S. D. Kumar, “Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits,” IEEE Transactions on Magnetics, vol. 54, no. 7, pp. 1–8, Jul. 2018 (Featured on front cover of July 2018 Issue).

51. S.D. Kumar, H. Thapliyal, and A. Mohammad, “FinSAL: FinFET Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 37, no.1, pp. 110–122, 2018.  

52. H. Thapliyal, R. K. Nath, and S. P. Mohanty, “Smart Home Environment for Mild Cognitive Impairment Population: Solutions to Improve Care and Quality of Life,” IEEE Consumer Electronics Magazine, vol. 7, no. 1, pp. 68–76, 2018.

53. H. Thapliyal, V. Khalus, and C. Labrado, “Stress Detection and Management: A Survey of Wearable Smart Health Devices”, IEEE Consumer Electronics Magazine, Vol. 6, No, 4, pp. 64-69, Oct 2017.

54. H. Thapliyal, A Mohammad, SD Kumar, F Sharifi, "Energy-efficient magnetic 4-2 compressor", Microelectronics Journal, vol. 67, pp.1-9, Sep 2017.

55. H. Thapliyal, “Spintronics and Reversible/Adiabatic Logic Based Ultra-Low-Power Computing and Memory Units for Digital Signal Processing”, Transactions on Techniques in STEM Education, vol.2, No. 3, pp. 84-90, April-June 2017

56. H. V. Jayashree, H. Thapliyal, and V. K. Agrawal, “Efficient Circuit Design of Reversible Square,” Transactions on Computational Science XXIX, pp 33-46, March 2017.

57. S.D. Kumar, H. Thapliyal, A. Mohammad, and K.S. Perumalla, “Design Exploration of Symmetric Pass Gate Adiabatic Logic for Energy-Efficient and Secure Hardware”, Integration, VLSI Journal, Vol. 58, pp. 369-377, June 2017. 

58. S. Greene, H. Thapliyal and A. Caban-Holt, "A Survey of Affective Computing for Stress Detection: Evaluating technologies in stress detection for better health," IEEE Consumer Electronics Magazine, vol. 5, no. 4, pp. 44-56, Oct. 2016.

59. F. Sharifi, A. Panahi, H. Sharifi, K. Navi, N. Bagherzadeh, and H. Thapliyal, “Design of quaternary 4–2 and 5–2 compressors for nanotechnology,” Computers & Electrical Engineering, vol. 56, pp. 64–74, Nov. 2016.

60. M. H. A. Khan, H. Thapliyal, and E. Munoz-Coreas, “Automatic synthesis of quaternary quantum circuits,” The Journal of Supercomputing, Volume 73, Issue 5, pp 1733–1759, May 2017

61. H. Thapliyal, “Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates,” in Transactions on Computational Science XXVII, M. L. Gavrilova and C. J. K. Tan, Eds. Springer Berlin Heidelberg, 2016, pp. 10–34.

62. S. Kotiyal and H. Thapliyal, “Design Methodologies for Reversible Logic Based Barrel Shifters,” Journal of Circuits, Systems and Computers, vol. 25, no. 02, p. 1650003, Feb. 2016.

63. H. Thapliyal, C. Labrado, and K. Chen, “Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines,” The Journal of Supercomputing, vol. 72, no. 3, pp. 1092–1124, Mar. 2016.

64. H. V. Jayashree, H. Thapliyal, et al., “Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier,” The Journal of Supercomputing, vol. 72, no. 4, pp. 1477–1493, Apr. 2016.

65. H. Thapliyal and C. Labrado, “Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing,” Electronics Letters, vol. 52, no. 6, pp. 464–466, Mar. 2016.

66. C. Labrado and H. Thapliyal, “Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing,” Electronics Letters, vol. 52, no. 19, pp. 1618–1620, 2016.

67. A. Roohi, H Thapliyal and R Demara, “Wire Crossing Constrained QCA Circuit Design using Bilayer Logic Decomposition”, Electronics Letters,  vol. 51, no. 21, pp. 1667–1669, Oct. 2015.

68. S. Kotiyal, H. Thapliyal and N. Ranganathan, “Reversible logic based multiplication computing unit using binary tree data structure", The Journal of Supercomputing,  vol. 71, no. 7, pp. 2668–2693, Mar. 2015.

69. S. Kotiyal, H. Thapliyal and N. Ranganathan, “Design of Reversible Adder-Subtractor and Its Mapping In Optical Computing Domain", Springer Transactions on Computational Science XXIV Lecture Notes in Computer Science, Vol. 8911, Jan 2015.

70. S. Kotiyal, H. Thapliyal and N. Ranganathan, “Efficient reversible NOR gates and their mapping in optical computing domain", Microelectronics Journal, Vol. 45, No.6, pp. 825-834, June 2014.

71. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits”, ACM Journal of Emerging Technologies in Computing Systems,Vol.9, No.3,pp. 17:1--17:31, Sep 2013.

72. H. Thapliyal,  N. Ranganathan and S.Kotiyal, “Design of Testable Reversible Sequential Circuits ", IEEE Transactions on VLSI, vol. 21, no.7,  pp.1201-1209, July 2013

73. H.Thapliyal, H. V. Jayashree, A. N. Nagamani, "Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder", Springer Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97

74. H. Thapliyal and N. Ranganathan, “Design of Reversible Sequential Circuits Optimizing Quantum Cost, Delay and Garbage Outputs", ACM Journal of Emerging Technologies in Computing Systems, Vol. 6, No. 4, Article 14, Dec 2010

75. H. Thapliyal and N. Ranganathan, “Reversible Logic Based Concurrently Testable Latches for Molecular QCA”, IEEE Transactions on Nanotechnology, vol. 9, No. 1, pp. 62-69, Jan 2010.

76. H. Thapliyal and M.B. Srinivas, “Efficient Reversible Logic Design of BCD Subtractors”, Springer Transactions on Computational Sciences Journal, Vol. 3, LNCS 5300, pp. 99-121, 2009.

77. H. Thapliyal and M.B Srinivas, “High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematic”, Transactions on Engineering, Computing and Technology, vol. 2, pp. 225-228, Dec 2004.

Selected Conferences / Workshops:

1. S. Sounak and H. Thapliyal, "Quantum Machine Learning for Anomaly Detection in Consumer Electronics,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024.

2. S. Sounak and H. Thapliyal, " Transfer Learning Based Hybrid Quantum Neural Network Model for Surface Anomaly Detection,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024.

3. T. Cultice, Md. S. H. Onim, A. Giani and H. Thapliyal, " Anomaly Detection for Real-World Cyber-Physical Security using Quantum Hybrid Support Vector Machines,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024.

4.  B. Gaur, T. Humble, and H. Thapliyal, " Residue Number System (RNS) based Distributed Quantum Addition,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024

5.  J. Clark, E. Raffel and H. Thapliyal, " Automated Generation of Dual Rail Adiabatic Gates from Binary Decision Diagrams,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024

6. M. T. Nasab, W. Yang and H. Thapliyal, " Energy-Efficient Power Attack-Resilient Adiabatic-MTJ-Based Nonvolatile CLB,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024

7. Md. S. H. Onim and H. Thapliyal, " Predicting Stress in Older Adults with RNN and LSTM from Time Series Sensor Data and Cortisol,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024

8. T. Bhattacharyya, A. Lohia, P. Ghosal, and H. Thapliyal, " WAFER: Wearable, Ambient-Aware Adversarial Fall Event Detection System using a RISC-V SoC Architecture,"  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2024

9. M. T. Nasab, W. Yang and H. Thapliyal, "Energy-Efficient Adiabatic MTJ/CMOS-Based CLB for Non-Volatile FPGA," 2024 IEEE 24th International Conference on Nanotechnology (NANO), Gijon, Spain, 2024, pp. 517-522, doi: 10.1109/NANO61778.2024.10628919.

10. J. Clark and H. Thapliyal, "Peephole Optimization for Quantum Approximate Synthesis," 2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, pp. 1-8, doi: 10.1109/ISQED60706.2024.10528701

11. J. Clark, T. S. Humble and H. Thapliyal, "GTQCP: Greedy Topology-Aware Quantum Circuit Partitioning," 2023 IEEE International Conference on Quantum Computing and Engineering (QCE), Bellevue, WA, USA, 2023, pp. 739-744, doi: 10.1109/QCE57702.2023.00089.

12. M. T. Nasab and H. Thapliyal, "Low-Power Adiabatic/MTJ LIM-Based XNOR/XOR Synapse and Neuron for Binarized Neural Networks," 2023 IEEE 23rd International Conference on Nanotechnology (NANO), Jeju City, Korea, Republic of, 2023, pp. 649-654, doi: 10.1109/NANO58406.2023.10231249.

13. Md. S. H. Onim and H. Thapliyal, “CASD-OA: Context-Aware Stress Detection for Older Adults with Machine Learning and Cortisol Biomarker,” in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville TN USA: ACM, Jun. 2023, pp. 103–108. doi: 10.1145/3583781.3590218.

14. T. Cultice, J. Clark, and H. Thapliyal, “Lightweight Hierarchical Root-of-Trust Framework for CAN-based 3D Printing Security,” in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville TN USA: ACM, Jun. 2023, pp. 215–216. doi: 10.1145/3583781.3590324.

15. J. Clark, T. Humble, and H. Thapliyal, “TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits,” in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville TN USA: ACM, Jun. 2023, pp. 587–592. doi: 10.1145/3583781.3590234.

16. B. Gaur, T. Humble, and H. Thapliyal, “Noise-Resilient and Reduced Depth Approximate Adders for NISQ Quantum Computing,” in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville TN USA: ACM, Jun. 2023, pp. 427–431. doi: 10.1145/3583781.3590315.

17. B. Gaur, E. Muñoz-Coreas, and H. Thapliyal, “A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n - 1) Adder,” in Proceedings of the Great Lakes Symposium on VLSI 2023, Knoxville TN USA: ACM, Jun. 2023, pp. 125–130. doi: 10.1145/3583781.3590205.

18. W. Yang, A. Degada and H. Thapliyal, "Adiabatic Logic-Based STT-MRAM Design for IoT," 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp.235-240

19. J. Clark and H. Thapliyal, " A Novel Approach to Quantum Circuit Partitioning," 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, pp. 450-451.

20. J. Clark and H. Thapliyal, "Edge Device Based Stress Detection for Older Adults with Cortisol Biomarker" 2022 IEEE International Conference on Consumer Electronics (ICCE), Jan 2022.

21. A. Degada, H. Thapliyal and S. P. Mohanty, "Smart Village: An IoT Based Digital Transformation," 2021 IEEE 7th World Forum on Internet of Things (WF-IoT), 2021, pp. 459-463, doi: 10.1109/WF-IoT51360.2021.9594980.

22. J. Clark, R. K. Nath and H. Thapliyal, "Machine Learning Based Prediction of Future Stress Events in a Driving Scenario," 2021 IEEE 7th World Forum on Internet of Things (WF-IoT), 2021, pp. 455-458, doi: 10.1109/WF-IoT51360.2021.9595098.

23. R. K. Nath and H. Thapliyal, "Wearable Health Monitoring System for Older Adults in a Smart Home Environment," 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, pp. 390-395, doi: 10.1109/ISVLSI51109.2021.00077

24. Z. Kahleifeh and H. Thapliyal, "Low-Energy and CPA-Resistant Adiabatic CMOS/MTJ Logic for IoT Devices," 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, pp. 314-319, doi: 10.1109/ISVLSI51109.2021.00064.

25. R. K. Nath, H. Thapliyal and T. S. Humble, "Quantum Annealing for Automated Feature Selection in Stress Detection," 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, pp. 453-457, doi: 10.1109/ISVLSI51109.2021.00089.

26. A. Degada and H. Thapliyal, “2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT,” Proceedings of the 2021 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2021. (Best Paper Award)

27. T. Cultice, D. Ionel and H. Thapliyal, “Smart Home Sensor Anomaly Detection Using Convolutional Autoencoder Neural Network”, Proceedings of the 2020 IEEE International Symposium on Smart Electronic Systems (iSES), Chennai, India, 2020, pp. 67-70. 

28. H. Thapliyal, “Quantum Machine Learning for Predictive Analytics”, Workshop on Quantum Computing Opportunities in Renewable Energy (IEEE International Conference on Quantum Computing and Engineering), Oct 2020.

29. H. Thapliyal, E. Muñoz-Coreas and V. Khalus, "Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing," 2020 IEEE 38th International Conference on Computer Design (ICCD), Hartford, CT, USA, 2020, pp. 5-8, doi: 10.1109/ICCD50377.2020.00014.

30. H. Thapliyal and S. D. Kumar, "Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ," 2020 IEEE 38th International Conference on Computer Design (ICCD), Hartford, CT, USA, 2020, pp. 25-28, doi: 10.1109/ICCD50377.2020.00019.

31. E. Munoz-Coreas and H. Thapliyal, “Quantum Carry Lookahead Adders for NISQ Machines”, The 2nd International Workshop on Quantum Resource Estimation, QRE2020, co-located with International Symposium on Computer Architecture (ISCA) 2020, May 2020.

32. T. Cultice, C. Labrado and H. Thapliyal, "A PUF Based CAN Security Framework," 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020, pp. 602-603, doi: 10.1109/ISVLSI49217.2020.00094. 

33. W. Yang and H. Thapliyal, "Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing," 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020, pp. 312-315, doi: 10.1109/ISVLSI49217.2020.00064.

34. Z.  Kahleifeh and H. Thapliyal, “2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices,” Proceedings of the IEEE 6th World Forum on Internet of Things (WF-IoT), New Orleans, June 2020.  (Best Paper Award and Outstanding Student Paper Award)

35. R. K. Nath and H. Thapliyal, "PPG Based Continuous Blood Pressure Monitoring Framework for Smart Home Environment," 2020 IEEE 6th World Forum on Internet of Things (WF-IoT), New Orleans, LA, USA, 2020, pp. 1-6, doi: 10.1109/WF-IoT48130.2020.9221386.

36. C. Terrell and H. Thapliyal, “Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications,” Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2020.

37. A. Degada and H. Thapliyal, “Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices,” Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2020.

38. R. Nath, H. Thapliyal and A. Caban-Holt, “Validating Physiological Stress Detection Model Using Cortisol as Stress Bio Marker,” Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2020.

39. H. Thapliyal and Z. Kahleifeh, “Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing,” Proceedings of the 2019 Great Lakes Symposium on VLSI, Tysons Corner, VA, USA, 2019, pp. 525–530. (Invited Panelist Position Paper)

40. Z. Khaliefeh and H. Thapliyal, “Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications”, Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, Miami, FL, USA, July 2019, pp. 414-418.

41. E. Munoz-Coreas, and H. Thapliyal, “Design of Quantum Circuits for Cryptanalysis and Image Processing Applications”, Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, Miami, FL, USA, July 2019, pp. 360-365.

42. Y. Takahashi, H. Koyasu, S. D. Kumar and  H. Thapliyal, “Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function”, Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, Miami, FL, USA, July 2019, pp. 443-446.

43. R. Nath, H. Thapliyal and A. Caban-Holt, “Towards Photoplethysmogram based Non-Invasive Blood Pressure Classification”, Proceedings of the 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Hyderabad, India, 2018, pp. 37-39. 

44. H. Thapliyal, N. Ratajczak, O. Wendroth and C. Labrado, “Amazon Echo Enabled IoT Home Security System for Smart Home Environment”, Proceedings of the 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Hyderabad, India, 2018, pp. 31-36. 

45. Z. Khaliefeh, S. D. Kumar, and H. Thapliyal, “Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing”,  Proceedings of the 2018 IEEE International Conference on Rebooting Computing (ICRC), McLean, VA, USA, 2018, pp. 1-6. 

46. E. Munoz-Coreas and H. Thapliyal, “T-count Optimized Quantum Circuits for Bilinear Interpolation”, Proceedings of the  2018 Ninth International Green and Sustainable Computing Conference (IGSC), Pittsburgh, PA, USA, 2018, pp. 1-6.

47. S. D. Kumar, C. Labrado, R. Badhan, H. Thapliyal, V. Singh, “Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices”, Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, July 2018, pp. 697-702.

48. R. Nath, R. Bajpai and H. Thapliyal, “IoT Based Indoor Location Detection System for Smart Home Environment,” Proceedings of the 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2018, pp.1-3.

49. H. Thapliyal and S.D. Kumar, “Energy-Recovery Based Hardware Security Primitives for Low-Power Embedded Devices”, Proceedings of the 2018 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, Jan 2018, pp. 1-6.

50. H. Thapliyal, T.S.S. Varun, S.D. Kumar, “Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices”, Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, July 2017, pp. 621-626.

51. H. Thapliyal, T. S. S. Varun, E. Munoz-Coreas, K. A. Britt, and T. S. Humble, “Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth,” in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017, pp. 123–128.

52. S. D. Kumar and H. Thapliyal, “Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks,” in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017, pp. 117–122.

53. H. Thapliyal, T.S.S. Varun, S.D. Kumar, “Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits”, 2017 IEEE International Conference on Rebooting Computing (ICRC), Washington D.C., Nov 2017, pp.1-4.

54. H. Thapliyal, T.S.S. Varun, S.D. Kumar, “Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices”, Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, July 2017, pp. 621-626.

55. E. Munoz-Coreas, and H. Thapliyal, “Design of Quantum Circuits for Galois Field Squaring and Exponentiation”, Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, July 2017, pp. 68-73.

56. F. Sharifi and H. Thapliyal , “Energy-Efficient Magnetic Circuits Based on Nanoelectronic Devices”, 2017 IEEE International Symposium on Circuits & Systems, Baltimore, MD, May 2017, pp. 1-4.

57. C. Labrado,  H. Thapliyal, and F. Lombardi, “Design of Majority Logic Based Approximate Arithmetic Circuits”, 2017 IEEE International Symposium on Circuits & Systems, Baltimore, MD, May 2017, pp. 1-4.

58. H. Thapliyal, T.S.S. Varun, S.D. Kumar, “UTB-SOI Based Adiabatic Computing for Low-Power and Secure IoT Devices”, Proceedings of the 12th Annual Cyber and Information Security Research Conference, Oak Ridge, April 2017 (Best Paper Award)

59. E. Munoz-Coreas and H. Thapliyal, “Resource Efficient Design of Quantum Circuits for Galois Field Squaring and Exponentiation”, 2017 Design Automation Conference (DAC), Work-in-Progress Session, Austin, June 2017

60. H. Thapliyal, T.S.S. Varun, S.D. Kumar, “Adiabatic Computing for Low Power and DPA Resistant Lightweight Cryptography for IoT Applications”, 2017 Design Automation Conference (DAC), Work-in-Progress Session, Austin, June 2017

61. V.  Mishra and H. Thapliyal, “Heuristic based Majority/minority Logic Synthesis for Emerging Technologies”, Proceedings of the 30th IEEE International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 2017.

62. S. D. Kumar, H. Thapliyal, A. Mohammad, V. Singh, and K. S. Perumalla, “Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic,” Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI, 2016, pp. 308–313.

63. S. Greene, H. Thapliyal, and D. Carpenter, " IoT Based Fall Detection for Smart Home Environments”, Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, Gwalior, Dec 2016

64. P. Sundaravadivel, S.P. Mohanty, E. Kougianos, V. P. Yanambaka, and H. Thapliyal,” Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems”, Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, Gwalior, Dec 2016

65. S. D. Kumar, H. Thapliyal, and A. Mohammad, “FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices,” Proceedings of the 2016 IEEE International Conference on Rebooting Computing (ICRC), 2016, pp. 1–8.

66. H. Thapliyal, T. S. S. Varun, and E. Munoz-Coreas, “Quantum Circuit Design of Integer Division Optimizing Ancillary Qubits and T-Count,” Proceedings of the 16th Asian Quantum Information Science Conference (AQIS), Taiwan, Sep 2016

67. S. D. Kumar and H. Thapliyal, “QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function,” Proceedings of the 11th Annual Cyber and Information Security Research Conference, 2016, p. 24.

68. S. Maynard, H. Thapliyal, and A. Caban-Holt, "Smart Home System for Patients with Mild Cognitive Impairment", Proceedings of the International Conference on Computational Science and Computational Intelligence (CSCI), Dec 2015

69. M. S. Ijjada, H. Thapliyal, A. Caban-Holt, “Evaluation of Wearable Head Set Devices In Older Adult Populations for Research”, Proceedings of the International Conference on Computational Science and Computational Intelligence (CSCI), Dec 2015

70. C. Labrado, H. Thapliyal, and R. F. Demara, “Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing,” Proceedings of the 2015 IEEE International Symposium on Nanoelectronic and Information Systems, 2015, pp. 107–111.

71. H. Thapliyal, “Circuit design of garbageless reversible multiplier for quantum computing”,  Proceedings of the Quantum Programming and Circuits Workshop, Waterloo, June 2015

72. H. Thapliyal and C. Labrado, “Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing”,  Proceedings of the 24th Annual Single Event Effects (SEE) Symposium/ Military and Aerospace Programmable Logic Devices (MAPLD) Workshop, San Diego, May 2015

73. M. H. A. Khan and H. Thapliyal, "Reversible logic based mapping of quaternary sequential circuits using QGFSOP expression,' Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, July 2015,  pp. 297-302.

74. H.V. Jayashree, H. Thapliyal and V. Agrawal, “Design of Dedicated Reversible Quantum Circuitry for Square Computation”,  Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 551-556.

75. S. Kotiyal H. Thapliyal and N. Ranganathan, “Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits”, Proceedings of the 27th International Conference on VLSI Design (VLSI Design), Mumbai, India, Jan 2014, pp. 545-550.

76. H.Thapliyal, A. Bhatt and N. Ranganathan, “A New CRL Gate As a Super Class of Fredkin Gate for Design of Reversible Barrel Shifter",   Proceedings of the 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, Aug 2013, pp. 1067-1070. 

77. H.Thapliyal and N. Ranganathan, “Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies",   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, pp. 5-6.  (Best  Paper Award)

78.  S.Kotiyal, H.Thapliyal and N. Ranganathan,  “Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates ",   Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, Aug 2012, March 2012, pp. 207-212.

79. S.Kotiyal, H.Thapliyal and N. Ranganathan, "Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder",   Proceedings of the Design Automation and Test in Europe (DATE), Dresden, Germany, March 2012, pp. 721-726.

80. H. Thapliyal and N. Ranganathan, “A new design of the reversible subtractor circuit”, Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp.1430-1435.

81. S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Design of a reversible bidirectional barrel shifter”, Proceedings of the   11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, 463-468.

82. M. Nachtigal, H. Thapliyal, and N. Ranganathan, “Design of a reversible floating-point adder architecture”, Proceedings of the  11th IEEE International Conference on Nanotechnology (IEEE NANO), Portland, Oregon, August 2011, pp. 451-456.

83. H. Thapliyal and N. Ranganathan, “ A New Reversible Design of BCD Adder", Proceedings  of  Design Automation and Test in Europe (DATE), Grenoble, France, March 2011, pp.1180-1183.

84. H. Thapliyal, N. Ranganathan and R. Ferreira, “Design of a Comparator Tree Based on Reversible Logic", Proceedings of the 10th IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010, pp. 1113-1116.   

85. H. Thapliyal and N.Ranganathan, “Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits", Proceedings  of the 10th  IEEE International Conference on Nanotechnology  (IEEE NANO),Seoul, Korea, Aug 2010, pp.217-222.   

86. M. Nachtigal, H. Thapliyal and N. Ranganathan,  "Design of a Reversible Single Precision Floating Point Multiplier Based on Operand Decomposition",   Proceedings of the 10th  IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.233-237.    

87. S.  Kotiyal, H. Thapliyal and  N. Ranganathan,  “Design of A Ternary Barrel Shifter Using Multiple-Valued Reversible Logic", Proceedings  of the 10th  IEEE International Conference on Nanotechnology (IEEE NANO), Seoul, Korea, Aug 2010,pp.1104-1108.      

88. H. Thapliyal and N. Ranganathan, "Design of Reversible Latches Optimized for Quantum Cost,Delay and Garbage Outputs", Proceedings of  the 23rd International Conference on  VLSI Design (VLSI Design) , Bangalore, India,  Jan 2010,pp.235-240.

89. H. Thapliyal and N. Ranganathan, ”Bit Conserving Logic as a Potential Integration Platform for Hybrid Molecular & Nanoscale CMOS-Based Architectures”, Proceedings  of the 2009 Nanoelectronic Devices for Defense & Security (NANO-DDS) Conference, Fort Lauderdale, Sept 2009.

90. H. Thapliyal and N. Ranganathan, “Concurrently Testable FPGA Design for Molecular QCA Using Conservative Reversible Logic Gate”, Proceedings of the International Symposium on Circuits and Systems (ISCAS), Taipei, May 2009, pp. 1815 - 1818.  

91. H. Thapliyal and N. Ranganathan, “Design of Efficient Reversible Binary Subtractors Based on A New Reversible Gate ",   Proceedings  of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, May 2009, pp.239-234.

92. H. Thapliyal and N. Ranganathan, " Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits",  Proceedings of the 22nd International Conference on  VLSI Design (VLSI Design), Delhi, India, Jan 2009, pp.511-516.

93. H. Thapliyal and N. Ranganathan, "Testable Reversible Latches for Molecular QCA", Proceedings of the 8th International Conference on Nanotechnology (IEEE NANO), Arlington, TX, Aug 2008. pp. 699-702 (Invited Paper).

94. H. Thapliyal and A. P. Vinod, “Design of Reversible Sequential Elements with Feasibility of Transistor Implementation”, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp. 625-628.

95. H. Thapliyal and A. P. Vinod, “Designing Efficient Online Testable Reversible Adders with New Reversible Gate”, Proceedings  of the IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 2007, pp.1085-1088

96. H. Thapliyal et al., "Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and its Reversible Logic Implementation", Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico, Aug 2006, pp. 438-442 (Best Student Paper Award Finalist). 

97. H. Thapliyal and M.B Srinivas, "Reversible Logic Implementation of BCD Subtractor for IEEE 754r Format", Proceedings of the 15th ACM SIGDA International Workshop on Logic & Synthesis (IWLS ), Colorado, USA, June 7-9, 2006.

98. H. Thapliyal and A. P. Vinod, "Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures," Proceedings of the APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, Singapore, 2006, pp. 418-421.

99. H. Thapliyal and M. B. Srinivas, "Novel Reversible Multiplier Architecture Using Reversible TSG Gate," Proceedings of the IEEE International Conference on Computer Systems and Applications, 2006., Dubai, UAE, 2006, pp. 100-103. doi: 10.1109/AICCSA.2006.205074

100. H. Thapliyal and M. Zwolinski, "Reversible Logic to Cryptographic Hardware: A New Paradigm", Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Puerto Rico, Aug 2006, pp. 342-346 (Best Student Paper Award Finalist).   

101. H. Thapliyal and M. B. Srinivas "Design of Wallace tree multiplier and other components of a quantum ALU using reversible TSG gate", Proc. SPIE 6264, Quantum Informatics 2005, 62640H (31 May 2006)

102. H. Thapliyal and S. K. Gupta, "Design of Novel Reversible Carry Look-Ahead BCD Subtractor," Proceedings of the 9th International Conference on Information Technology (ICIT'06), Bhubaneswar, 2006, pp. 253-258, doi: 10.1109/ICIT.2006.44.

103. N. Gopi, K. Kumar, H. Thapliyal and M. Srinivas, “Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture," Proceedings of the 2006 IEEE International Conference on Computer Systems and Applications, Dubai, UAE, 2006 pp. 88-92.

104. H. Thapliyal and M.B. Srinivas, “The New BCD Subtractor and Its Reversible Logic Implementation", Springer-Verlag Lecture Notes in Computer Science, Proceedings of the 11th Asia-Pacific Computer Systems Architecture Conference - ACSAC, Vol. 4186/2006, pp. 469-475, Sep 2006 

105. H. Thapliyal and M.B. Srinivas et al., “Modified Montgomery Modular Multiplication Using 4:2 Compressor And CSA Adder", Proceedings of the  3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA) , Kuala Lumpur, Malaysia, Jan 2006, pp. 414-417.  

106. H. Thapliyal, S. Kotiyal and M.B. Srinivas, “Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format”, Proceedings of the 19th  IEEE/ACM International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 4-7, 2006, pp. 387-392. 

107. H. Thapliyal, S. Kotiyal and M. B. Srinivas, "Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics," Proceedings of the 48th Midwest Symposium on Circuits and Systems, 2005., Covington, KY, 2005, pp. 1462-1465 Vol. 2.

108. H. Thapliyal and M. B. Srinivas, "Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU," Proceedings of the 2005 5th International Conference on Information Communications & Signal Processing, Bangkok, 2005, pp. 1425-1429.

109. H. Thapliyal and M. B. Srinivas, "Novel design and reversible logic synthesis of multiplexer based full adder and multipliers," Proceedings of the 48th Midwest Symposium on Circuits and Systems, 2005., Covington, KY, 2005, pp. 1593-1596. 

110. H. Thapliyal and M.B. Srinivas, “Novel Reversible “TSG” Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures”, Springer-Verlag Lecture Notes in Computer Science , Proceedings of the 10th Asia-Pacific Computer Systems Architecture Conference - ACSAC, vol. 3740/2005, pp. 775-786, October 2005.  

111. H. Thapliyal, P. Gopineedi and M. B. Srinivas, "A low power decomposed hierarchical multiplier architecture embedding multiplexer based full adders," Proceedings of the 48th Midwest Symposium on Circuits and Systems, 2005., Covington, KY, 2005, pp. 1485-1488 Vol. 2, doi: 10.1109/MWSCAS.2005.1594394.

112. H. Thapliyal and M.B. Srinivas, “An Efficient Method of Elliptic Curve Encryption Using Ancient Indian Vedic Mathematics", Proceedings of the 48th IEEE MIDWEST Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio, USA, August 7-10, 2005, pp. 826-829. 

113. H. Thapliyal and M. B. Srinivas, "VLSI implementation of RSA encryption system using ancient Indian Vedic mathematics," Proc. SPIE 5837, VLSI Circuits and Systems II, June 2005. 

114. H. Thapliyal and M. B. Srinivas, "An extension to DNA based Fredkin gate circuits: design of reversible sequential circuits using Fredkin gates," Proc. SPIE 6050, Optomechatronic Micro/Nano Devices and Components, 60500O, Dec 2005.

115. H. Thapliyal, M. B. Srinivas, "The need of DNA computing: reversible design of adders and multipliers using Fredkin gate," Proc. SPIE 6050, Optomechatronic Micro/Nano Devices and Components, 605010, Dec 2005.

116. H.  Thapliyal, M. B. Srinivas and M. Zwolinski, “A Beginning in the Reversible Logic Synthesis of Sequential Circuits,” Proceedings of NASA Military and Aerospace Programmable Logic Devices (MAPLD) International Conference, Sep 2005.  

117. H. Thapliyal and M.B Srinivas, "A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits," Proceedings of the 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM 2005), Tokyo, Japan, September 5-6, 2005.

118. H. Thapliyal, R. V. Kamala and M. Srinivas, "RSA encryption/decryption in wireless networks using an efficient high speed multiplier," Proceedings of the 2005 IEEE International Conference on Personal Wireless Communications, 2005. ICPWC 2005., New Delhi, India, 2005, pp. 417-419, doi: 10.1109/ICPWC.2005.1431378.

US PATENT / PATENT APPLICATIONS / INVENTION DISCLOSURES:

1. H. Thapliyal, W. Yanga and A. Degada, “Novel Writing Circuitries for MTJ/CMOS Circuits”, US Provisional Appln 63/521,794, June 2023

2. Architecture for generating physically unclonable function response, H. Thapliyal and C. Labrado, US U.S. Patent US11206146B2, Dec 2021.

3. Adiabatic Logic in Memory Architecture, H. Thapliyal and S. Dinesh Kumar, U.S. Patent No. 10,868,534. 15 Dec. 2020.

4. Conservative Logic Element for Design of Quantum Dot Cellular Automata Circuits, N. Ranganathan and H. Thapliyal, US Patent 7880496, 2011

TUTORIALS AND BOOK CHAPTERS:

1. R. K. Nath, H. Thapliyal, and T. S. Humble, “Quantum Annealing for Real-World Machine Learning Applications,” in Quantum Computing: Circuits, Systems, Automation and Applications, H. Thapliyal and T. Humble, Eds., Cham: Springer International Publishing, 2024, pp. 157–180. doi: 10.1007/978-3-031-37966-6_9.

2. H. Thapliyal and E. Munoz-Coreas, “Design of Quantum Circuits,” IEEE International Symposium on Smart Electronic Systems, Dec 2022

3. E. Munoz-Coreas and H. Thapliyal, “Everything You Always Wanted to Know about Quantum Circuits,” in Wiley Encyclopedia of Electrical and Electronics Engineering. John Wiley & Sons, Ltd, 2022, pp. 1–17. [Online]. Available: https://onlinelibrary.wiley.com/doi/abs/10. 1002/047134608X.W8440

4. H. Thapliyal, S.P. Mohanty and R. Bajpai, “Consumer Technologies for Smart Cities to Smart Villages”, IEEE International Conference on Consumer Electronics, January 2021.

5. H.Thapliyal and N. Ranganathan, “Reversible Logic: Basics, Prospects in Emerging Nanotechnologies and Challenges in Future”, Tutorial at 55th International Midwest Symposium on Circuits and systems (IEEE MWSCAS 2012), Boise, Idaho, August 5-8, 2012.

6. H.Thapliyal and N. Ranganathan, “Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future”, Tutorial at 25th International Conference on VLSI Design (VLSI Design), Hyderabad, India, Jan 2012, pp. 13-15.

7. H. Thapliyal, N. Ranganathan and S.Kotiyal, “Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits", Springer Lecture Notes on Computer Science State-of the-Art-Survey Series Special Volume on Field-Coupled Nanocomputing, 2014, pp. 133-172.